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march 2007 hy[b/i]39s256[40/80/16]0ft(l) hy[b/i]39s256[40/80/16]0fe(l) hyb39s256[40/80/16]0ff(l) hyb39s256407fe 256-mbit synchronous dram sdram internet data sheet rev. 1.3
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram qag_techdoc_rev400 / 3.2 qag / 2006-08-07 2 03292006-tmtk-jfeu hy[b/i]39s256[40/80/16]0ft(l), hy[b/i]39s256[40/80/16]0fe(l) , hyb39s256[40/80/16]0ff(l) , hyb39s256407fe revision history: 2007-03, rev. 1.3 page subjects (major chan ges since last revision) all adapted internet edition 19 corrected mode register definition 25 corrected idd6 for low power components 4 added hyi39s256160ft-7, hyi39s256160fe-7, hyi39s256800fe-7 and hyi39s256800ft-7, hyb39s256407fe-7, hyb39s256160ft-6 7 changed ?page length = 2048/1024/512 bi ts? to ?2048/1024/512 addresses? previous revision: 2006-09, rev. 1.21 all qimonda update previous revision: 2006-05, rev. 1.2
internet data sheet rev. 1.3, 2007-03 3 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 1overview this chapter lists all main features of the product family hyb39s256[400/800/160]f[e/t/f](l) and the ordering information. 1.1 features ? fully synchronous to positive clock edge ? 0 to 70 c standard operating temperature ? -40 to 85 c industrial operating temperature ? four banks controlled by ba0 & ba1 ? programmable cas latency: 2 & 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 and full page ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control (x4, x8) ? data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? power down and clock suspend mode ? 8192 refresh cycles / 64 ms (7.8 s) ? random column address every clk (1-n rule) ? single 3.3 v 0.3 v power supply ? lvttl interface versions ? packages: ? p(g)?tsopii?54 (400mil width) ? pg?tfbga?54 table 1 performance 1.2 description the hyb39s256[400/800/160]f[e/t/f](l) are four bank synchronous dr ams organized as 4 banks x 16 mbit x4, 4 banks x 8 mbit x8 and 4 banks x 4 mbit x16 respectively. these synchronous devices achieve high speed data transfer rates for cas latencies by employing a chip architecture that prefetch es multiple bits and then sync hronizes the output data to a system clock. the chip is fabric ated with qimonda?s advanced 0.11- m 256-mbit dram process technology. the device is designed to comply with all industry standard s set for synchronous dram products, both electrically and mechanically. all of the control, address, da ta input and output circuits are synchroni zed with the positive edge of an externa lly supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless da ta rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh oper ation are supported. these devices operate with a single 3.3 v 0.3 v power supply. all 256-mbit components are available in p(g)?tsopii?54 and pg ?tfbga?54 packages. poduct type speed code ?6 ?7 unit speed grade pc166?333 pc133?222 ? max. clock frequency @cl3 f ck3 166 143 mhz t ck3 67ns t ac3 5.4 5.4 ns @cl2 t ck2 7.5 7.5 ns t ac2 5.4 5.4 ns
internet data sheet rev. 1.3, 2007-03 4 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 2 ordering information table 3 ordering information for rohs compliant products product type speed grade description package standard operating temperature hyb39s256400ft-7 pc133-222-520 143mhz 64m x 4 sdram p-tsopii-54 hyb39s256400ftl-7 hyb39s256800ft-7 143mhz 32m x 8 sdram hyb39s256800ftl-7 hyb39s256160ft-7 143mhz 16m x 16 sdram hyb39s256160ftl-7 hyb39s256160ft-6 166mhz 16m x 16 sdram industrial operating temperature hyi39s256800ft-7 pc133-222-520 143mhz 32m x 8 sdram p-tsopii-54 hyi39s256160ft-7 143mhz 16m x 16 sdram product type speed grade description package note standard operating temperature HYB39S256407FF-7 pc133-222-520 143mhz 64m x 4 sdram pg-tfbga-54 1) hyb39s256400fe-7 pg-tfbga-54 hyb39s256400fe-7 pg-tsopii-54 hyb39s256400ffl-7 pg-tfbga-54 hyb39s256400fel-7 pg-tsopii-54 hyb39s256800ff-7 143mhz 32m x 8 sdram pg-tfbga-54 hyb39s256800fe-7 pg-tsopii-54 hyb39s256800ffl-7 pg-tfbga-54 hyb39s256800fel-7 pg-tsopii-54 hyb39s256160ff-7 143mhz 16m x 16 sdram pg-tfbga-54 hyb39s256160fe-7 pg-tsopii-54 hyb39s256160ffl-7 pg-tfbga-54 hyb39s256160fel-7 pg-tsopii-54 hyb39s256160ff-6 166mhz 16m x 16 sdram pg-tfbga-54 hyb39s256160fe-6 pg-tsopii-54 hyb39s256160ffl-6 pg-tfbga-54 hyb39s256160fel-6 pg-tsopii-54
internet data sheet rev. 1.3, 2007-03 5 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram industrial operating temperature hyi39s256800fe-7 pc166-333-520 143mh z 32m x 8 sdram pg-tsopii-54 1) hyi39s256160fe-7 143mhz 16m x 16 sdram 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed grade description package note
internet data sheet rev. 1.3, 2007-03 6 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 2 pin configuration this chapter contains the pin configuration tabl e and the tsop and fbga package drawing for the 4, 8, 16 organization of the sdram. 2.1 pin description listed below are the pin configurations sect ions for the various signals of the sdram. table 4 pin configuration of the sdram ball no. name pin type buffer type function clock signals 4/ 8/ 16 organization 38,2f clk i lvttl clock signal ck 37,3f cke i lvttl clock enable control signals 4/ 8/ 16 organization 18, 8f ras ilvttl row address strobe (ras), column address strobe (cas), write enable (we) 17, 7f cas ilvttl 16, 9f we ilvttl 19, 9g cs ilvttl chip select address signals 4/ 8/ 16 organization 20, 7g ba0 i lvttl bank address signals 1:0 21, 8g ba1 i lvttl 23, 7h a0 i lvttl address signal 9:0, address signal 10/auto precharge 24,8h a1 i lvttl 25, 8j a2 i lvttl 26, 7j a3 i lvttl 29, 3j a4 i lvttl 30, 2j a5 i lvttl 31, h a6 i lvttl 32, 2h a7 i lvttl 33, 1h a8 i lvttl 34, 3g a9 i lvttl 22, 9h a10 i lvttl 35,2g a11 i lvttl 36, 1g a12 i lvttl
internet data sheet rev. 1.3, 2007-03 7 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram data signals 4 organization 5, 8b dq0 i/o lvttl data signal bus [15:0] 11, 8d dq1 i/o lvttl 44, 2d dq2 i/o lvttl 50, 2b dq3 i/o lvttl data signals 8 organization 2, 8a dq0 i/o lvttl data signal bus [15:0] 5, 8b dq1 i/o lvttl 8, 8c dq2 i/o lvttl 11, 8d dq3 i/o lvttl 44, 2d dq4 i/o lvttl 47, 2c dq5 i/o lvttl 50, 2b dq6 i/o lvttl 53, 2a dq7 i/o lvttl data signals 16 organization 2, 9a dq0 i/o lvttl data signal bus [15:0] 4, 9b dq1 i/o lvttl 5, 8b dq2 i/o lvttl 7, 9c dq3 i/o lvttl 8, 8c dq4 i/o lvttl 10, 9d dq5 i/o lvttl 11, 8d dq6 i/o lvttl 13, 9e dq7 i/o lvttl 42, 1e dq8 i/o lvttl 44, 2d dq9 i/o lvttl 45, 1d dq10 i/o lvttl 47, 2c dq11 i/o lvttl 48, 1c dq12 i/o lvttl 50, 2b dq13 i/o lvttl 51, 1b dq14 i/o lvttl 53, 2a dq15 i/o lvttl data mask 4/ 8 organization 39, 1f dqm i/o lvttl data mask data mask 16 organization 39, 1f udqm i/o lvttl data mask upper byte 15, 8e ldqm i/o lvttl data mask lower byte power supplies 4/ 8/ 16 organization 3b, 3d, 7a, 7c v ddq pwr ? power supply ball no. name pin type buffer type function
internet data sheet rev. 1.3, 2007-03 8 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 7e, 9a, 9j v dd pwr ? power supply 3a, 3c, 7b, 7d v ssq pwr ? power supply ground for dqs 1j, 1a, 3e v ss pwr ? power supply ground not connected 4 organization 2, 4, 7, 8, 10, 13, 15, 40, 42, 45, 47, 48, 51, 53, 1b, 1c, 1d, 1e, 2a, 2c, 2e, 8a, 8c, 8e, 9b, 9c, 9d, 9e nc nc ? not connected not connected 8 organization 7, 10, 13, 15, 40, 42, 45, 48, 51, 1b, 1c, 1d, 1e, 2e, 8e, 9b, 9c, 9d, 9e nc nc ? not connected not connected 16 organization 40, 2e nc nc ? not connected ball no. name pin type buffer type function
internet data sheet rev. 1.3, 2007-03 9 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 2.2 package p(g)?tsopii?54 listed below are the pin outs of the tsop package. figure 1 pinouts p(g) ?tsopii?54 6 33 6 ' ' ' 4 $ $3 $ $ $ $ 6 ' ' 6 ' ' 4 ' 4 ' 4 6 6 6 4 ' 4 ' 4 6 ' ' 4 ' 4 ' 4 6 6 6 4 ' 4 6 ' ' /' 4 0 & $6 : ( 5 $6 & 6 % $ % $ % $ % $ & 6 5 $6 : ( & $6 1 & 6 ' ' 1 & 6 6 6 4 ' 4 1 & 6 ' ' 4 ' 4 1 & 6 6 6 4 ' 4 1 & 6 ' ' 4 6 ' ' $ $ $ $ $ $3 ' 4 6 ' ' 6 ' ' % $ % $ & 6 5 $6 : ( & $6 1 & 6 ' ' 1 & 6 6 6 4 ' 4 1 & 6 ' ' 4 1 & 1 & 6 6 6 4 ' 4 1 & 6 ' ' 4 6 ' ' $ $ $ $ $ $3 1 & 6 6 6 1 & $ $ $ $ $ 6 6 6 6 6 6 4 1 & ' 4 6 ' ' 4 1 & 1 & 6 6 6 4 1 & ' 4 6 ' ' 4 1 & 6 6 6 1 & & / . ' 4 0 & . ( $ $ $ $ $ $ & . ( ' 4 0 & /. 1 & 6 6 6 1 & 6 '' 4 ' 4 1 & 6 6 6 4 ' 4 1 & 6 '' 4 ' 4 1 & 6 6 6 4 6 6 6 $ $ $ $ $ ' 4 6 6 6 6 6 6 $ $ $ & . ( 8 ' 4 0 & /. 1 & 6 6 6 ' 4 6 ' '4 ' 4 ' 4 6 6 6 4 ' 4 ' 4 6 ' '4 ' 4 ' 4 6 6 6 4 6 6 6 $ $ $ $ $ ' 4 7 6 2 3 , , p l o [ p l o p p s l w f k 0 [ 0 [ 0 [
internet data sheet rev. 1.3, 2007-03 10 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 2.3 package pg?tfbga?54 listed below are the ball outs of the tfbga package. ? figure 2 ?ballout for 16 components, p-tfbga-54 (top view)? on page 10 ? figure 3 ?ballout for 8 components, pg-tfbga-54 (top view)? on page 11 ? figure 4 ?ballout for 4 components, pg-tfbga-54 (top view)? on page 12 figure 2 ballout for 16 components, p-tfbga-54 (top view) 0 3 3 ' $ 6 6 6 4 8 ' 4 0 & / . ' 4 ' 4 ' 4 ' 4 ' 4 6 ' ' 4 6 6 6 4 6 ' ' 4 6 6 6 6 6 6 $ $ $ $ $ & . ( $ $ ' 4 ' 4 ' 4 6 6 6 % $ ' 4 ' 4 ' 4 6 ' ' /' 4 0 ' 4 6 6 6 4 6 ' ' 4 6 6 6 4 6 ' ' % $ $ $ $ 6 ' ' 6 ' ' 4 ' 4 ' 4 ' 4 ' 4 $ % & ' ) * + - ( & $6 5 $6 : ( $ $ & 6 1 &
internet data sheet rev. 1.3, 2007-03 11 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram figure 3 ballout for 8 components, pg-tfbga-54 (top view) 0 3 3 ' $ 6 6 6 4 ' 4 0 & / . 1 & 1 & 1 & 1 & ' 4 6 ' ' 4 6 6 6 4 6 ' ' 4 6 6 6 6 6 6 $ $ $ $ $ & . ( $ $ ' 4 ' 4 ' 4 6 6 6 % $ ' 4 ' 4 ' 4 6 ' ' 1 & ' 4 6 6 6 4 6 ' ' 4 6 6 6 4 6 ' ' % $ $ $ $ 6 ' ' 6 ' ' 4 1 & 1 & 1 & 1 & $ % & ' ) * + - ( & $6 5 $6 : ( $ $ & 6 1 &
internet data sheet rev. 1.3, 2007-03 12 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram figure 4 ballout for 4 components, pg-tfbga-54 (top view) 0 3 3 ' $ 6 6 6 4 ' 4 0 & / . 1 & 1 & 1 & 1 & 1 & 6 ' ' 4 6 6 6 4 6 ' ' 4 6 6 6 6 6 6 $ $ $ $ $ & . ( $ $ ' 4 1 & ' 4 6 6 6 % $ ' 4 1 & ' 4 6 ' ' 1 & 1 & 6 6 6 4 6 ' ' 4 6 6 6 4 6 ' ' % $ $ $ $ 6 ' ' 6 ' ' 4 1 & 1 & 1 & 1 & $ % & ' ) * + - ( & $6 5 $6 : ( $ $ & 6 1 &
internet data sheet rev. 1.3, 2007-03 13 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 3 functional description this chapter contains the functional description. table 5 truth table: operation command operation device state cke n-1 1)2) 1) v = valid, x = don?t care, l = low level, h = high level 2) cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provide d. cke n 1)2) dqm 1)2) ba0 ba1 1)2) ap= a10 1)2) addr. 1)2) cs 1 )2) ras 1)2) cas 1 )2) we 1)2) bank active idle 3) 3) this is the state of the banks designated by ba0, ba1 signals. hxxvvvllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3) hxxvlvlhll write with auto pre charge active 3) hxxvhvlhll read active 3) hxxvlvlhlh read with auto pre charge active 3) hxxvhvlhlh mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) l h x x x x h x x x lh h x clock suspend entry active h l x x x x x x x x power down entry (precharge or active standby) idle h l x x x x h x x x active l h h h clock suspend exit active 4) 4) power down mode can not be entered in a burst cycle. when this command asserted in the burst mode cycle device is in clock su spend mode. lhxxxxxxxx power down exit any (power down) lhxxxxhxxx lh h l data write/output enable active h x l x x x x x x x data write/output disable active h x h x x x x x x x
internet data sheet rev. 1.3, 2007-03 14 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 6 mode register definition (ba[1:0] = 00 b ) field bits type description bl [2:0] w burst length number of sequential bits per dq related to one read/write command. note: all other bit combinations are reserved 000 b 1 001 b 2 010 b 4 011 b 8 111 b full page (sequential burst type only) bt 3 burst type 0 b sequential 1 b interleaved cl [6:4] cas latency number of full clocks from read command to first data valid window. note: all other bit combinations are reserved. 010 b 2 011 b 3 tm [8:7] test mode note: all other bit combinations are reserved. 00 b mode register set wbl 9 write burst length 0 b burst write 1 b single bit write [12:10] reserved, set to zero 03%6 %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu z zzz %7 %/ &/ 70 :%/
internet data sheet rev. 1.3, 2007-03 15 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 7 burst length and sequence notes 1. for a burst length of two, a1-ai selects the two-data-el ement block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai sele cts the four-data-elem ent block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- el ement block; a0-a2 selects the first access with in the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst length starting column address order of accesses within a burst a2 a1 a0 type=sequential type=interleaved 2 ? ? 0 0?1 0?1 ? ? 1 1?0 1?0 4 ? 0 0 0?1?2?3 0?1?2?3 ? 0 1 1?2?3?0 1?0?3?2 ? 1 0 2?3?0?1 2?3?0?1 ? 1 1 3?0?1?2 3?2?1?0 8 0 0 0 0?1?2?3?4?5?6?7 0?1?2?3?4?5?6?7 0 0 1 1?2?3?4?5?6?7?0 1?0?3?2?5?4?7?6 0 1 0 2?3?4?5?6?7?0?1 2?3?0?1?6?7?4?5 0 1 1 3?4?5?6?7?0?1?2 3?2?1?0?7?6?5?4 1 0 0 4?5?6?7?0?1?2?3 4?5?6?7?0?1?2?3 1 0 1 5?6?7?0?1?2?3?4 5?4?7?6?1?0?3?2 1 1 0 6?7?0?1?2?3?4?5 6?7?4?5?2?3?0?1 1 1 1 7?0?1?2?3?4?5?6 7?6?5?4?3?2?1?0 fullpage n cn, cn+1, cn+2 .... not supported
internet data sheet rev. 1.3, 2007-03 16 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 4 electrical characteristics this chapter lists the el ectrical characteristics. 4.1 operating conditions this chapter describes the operating conditions. table 8 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol limit values unit note/ test condition min. max. input / output volt age relative to v ss v in , v out ? 1.0 +4.6 v ? voltage on v dd supply relative to v ss v dd ? 1.0 +4.6 v ? voltage on v ddq supply relative to v ss v ddq ? 1.0 +4.6 v ? operating temperature for hyb... t a 0+70 c? operating temperature for hyi... t a ?40 +85 c? storage temper ature range t stg ? 55 +150 c? power dissipation per sdram component p d ?1 w? data out current (short circuit) i out ?50ma?
internet data sheet rev. 1.3, 2007-03 17 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 9 dc characteristics table 10 input and output capacitances parameter symbol values unit note 1) / test condition 1) t a = 0 to 70 c min. max. supply voltage v dd 3.0 3.6 v 2) 2) all voltages are referenced to v ss i/o supply voltage v ddq 3.0 3.6 v 2) input high voltage v ih 2.0 v ddq + 0.3 v 2)3) 3) v ih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3 v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3 v. pulse width measured at 50 % points with amplitude measured peak to dc reference. input low voltage v il ? 0.3 +0.8 v 2)3) output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v 2) output low voltage ( i out = 4.0 ma) v ol ?0.4 v 2) input leakage current, any input (0 v < v in < v dd , all other inputs = 0 v) i il ? 5 +5 a? output leakage current (dqs are disabled, 0 v < v out < v ddq ) i ol ? 5 +5 a? parameter symbol values 1) 1) capacitance values are shown for ts op-54 packages. capacitance values fo r tfbga packages are lower by 0.5 pf unit note 2) 2) ta = 0 to 70 c; vdd,vddq = 3.3 v 0.3 v, f = 1 mhz min. max. input capacitances: ck, ck c i1 2.5 3.5 pf ? input capacitance (a0-a12, ba0, ba1, ras , cas , we , cs , cke, dqm) c i2 2.5 3.8 pf ? input/output capacitance (dq) c i0 4.0 6.0 pf ?
internet data sheet rev. 1.3, 2007-03 18 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 11 i dd conditions parameter symbol operating current one bank active, burst length = 1 i dd1 precharge standby current in power down mode i dd2p recharge standby current in non-power down mode i dd2n no operating current active state (max. 4 banks) i dd3n i dd3p burst operating current read command cycling i dd4 auto refresh current auto refresh command cycling i dd5 self refresh current (standard components) self refresh mode, cke=0.2v, t ck =infinity i dd6 self refresh current (low power components) self refresh mode, cke=0.2v, t ck =infinity
internet data sheet rev. 1.3, 2007-03 19 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram table 12 i dd specifications and conditions symbol ?6 ?7 unit note/ test condition 1)2) 1) currents values will be added when available. 2) t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v max. i dd1 t rc = t rc(min) , i o = 0 ma 100 80 ma 3)4) 3) these parameters depend on the cycle rate. all values are meas ured at 166 mhz for -6, at 133 mhz for -7 and -7.5 and at 100 m hz for - 8 components with the outputs open. input signals are changed once during t ck . 4) these parameters are measured with continuous data stream during read ac cess and all dq toggling. cl=3 and bl=4 is assumed an d the v ddq current is excluded. i dd2p cs = v ih (min.) , cke v il(max) 22ma 2) i dd2n cs = v ih (min.) , cke v ih(min) 26 22 ma 2) i dd3n cs = v ih(min) , cke v ih(min.) 40 35 ma 2) i dd3p cs = v ih(min) , cke v il(max.) 55ma 2) i dd4 ? 6557ma 2)3) i dd5 t rfc = t rfc(min) 168 142 ma 5) 5) t rfc = t rfc(min) ?burst refresh?, t rfc =7.8 s ?distributed refresh? t rfc = 7.8 s 2525ma? i dd6 ? 3 3 ma standard components 1.05 1.05 ma low power components 6) 6) 1.05 ma at 85 c, 1.00 ma at 60 c
internet data sheet rev. 1.3, 2007-03 20 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 4.2 ac characteristics this chapter lists t he ac characteristics. table 13 ac timing - absolute specifications ?7/-6 parameter symbol ?7 ?6 unit note 1)2)3) pc133?222 pc166?333 min. max. min. max. clock and clock enable clock frequency t ck ? ? ?7 ?7.5 ? ? ?6 ?7.5 ns ns cl3 cl2 access time from clock t ac ? ? 5.4 5.4 ? ? 5.4 5.4 ns ns cl3 cl2 3)4)5) clock high pulse width t ch 2.5 ? 2 ? ns ? clock low pulse width t cl 2.5 ? 2 ? ns ? transition time t t 0.3 1.2 0.3 1.2 ns ? setup and hold times input setup time t is 1.5 ? 1.5 ? ns 6) input hold time t ih 0.8 ? 0.8 ? ns 6) cke setup time t ck 1.5 ? 1.5 ? ns 6) cke hold time t ckh 0.8 ? 0.8 ? ns 6) mode register set-up to active delay t rsc 2? 2 ? t ck ? power down mode entry time t sb 07 0 6 ns? common parameters row to column delay time t rcd 15 ? 15 ? ns 7) row precharge time t rp 15 ? 15 ? ns 7) row active time t ras 37 100k 36 100k ns 7) row cycle time t rc 60 ? 60 ? ns 7) row cycle time during auto refresh t rfc 63 ? 60 ? ns ? activate(a) to activa te(b) command period t rrd 14 ? 12 ? ns 7) cas (a) to cas (b) command period t ccd 1? 1 ? t ck ? refresh cycle refresh period (8192 cycles) t ref ?64 ? 64 ms? self refresh exit time t srex 1? 1 ? t ck ? data out hold time t oh 3 ? 2.5 ? ns 3)5) read cycle data out to low impedance time t lz 0? 0 ?ns? data out to high impedance time t hz 37 3 6 ns? dqm data out disable latency t dqz ?2 ? 2 t ck ?
internet data sheet rev. 1.3, 2007-03 21 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram figure 5 measurement conditions for t ac and t oh write cycle last data input to precharge (write without auto precharge) t wr 14 ? 12 ? ns 8) last data input to activate (write with auto precharge) t dal(min.) ?? ? ? t ck 9) dqm write mask latency t dqw 0? 0 ? t ck ? 1) t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v, t t = 1 ns 2) for proper power-up see the operation section of this data sheet. 3) ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resi stive termination and with an input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 4) if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns has to be added to this parameter. 5) access time from clock t ac is 4.6 ns for pc133 components with no termination and 0 pf load, data out hold time t oh is 1.8 ns for pc133 components with no termination and 0 pf load. 6) if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 7) these parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the nu mber of clock cycles = specified value of timing per iod (counted in fracti ons as a whole number) 8) it is recommended to use two clock cycles between the last data- in and the precharge command in case of a write command witho ut auto- precharge. one clock cy cle between the last data-in and the precharge command is also supported, but re stricted to cycle times t ck greater or equal the specified twr value, where t ck is equal to the actual system clock time. 9) when a write command with auto precharge has been issued, a time of t dal(min) has be fullfilled before the next activate command can be applied. for each of the terms, if not already an integer, round up to the next highest integer. t ck is equal to the actual system clock time. parameter symbol ?7 ?6 unit note 1)2)3) pc133?222 pc166?333 min. max. min. max. clock 2.4 v 0.4 v in p u t is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd 50 pf i/o measurement conditions for t ac and t oh
internet data sheet rev. 1.3, 2007-03 22 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 5 package outlines this chapter contains the package outlines of the products. figure 6 package outline pg-tsopii-54-4 (top view) * 3 ; ? ? ? ? ? ? [ ? 0 [ ? ? [ 6 ( $ 7, 1 * 3 /$1 ( ? ? ? * $ 8 * ( 3 /$1 ( 0 $; 0 $; ? , q g h [ 0 d u n l q j ' r h v q r w l q f o x g h g d p e d u s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h s o d v w l f s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h s o d v w l f r u p h w d o s u r w u x v l r q r i p d [ s h u v l g h
internet data sheet rev. 1.3, 2007-03 23 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram figure 7 package outline p-tfbga-54-15 0 ? 0 , 1 0 $; $ 0 d u n l q j % d o o v l g h % d g 8 q l w 0 d u n l q j % 8 0 0 l g g o h r i 3 d f n d j h v ( g j h v ? 0 $; ? $ ? [ 0 & * 3 $ 6 ( $7, 1 * 3 /$1 ( [ $ % & % & 0 $; [ & &
internet data sheet rev. 1.3, 2007-03 24 03292006-tmtk-jfeu hy[b/i]39s256[40/80/1 6][0/7]f[e /t/f](l) 256-mbit synchronous dram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 package p(g)?tsopii?54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 package pg?tfbga?54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table of contents
edition 2007-03 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no even t be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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